The present invention relates to a tolerant input circuit including an input terminal provided with a voltage signal having voltage that is higher than the voltage from a power supply.
There may be cases when a voltage signal having voltage that is higher than the voltage from a power supply is applied to a semiconductor integrated circuit. To ensure that the semiconductor integrated circuit functions normally in such a case, the semiconductor integrated circuit incorporates a tolerant input circuit. The tolerant input circuit includes a step-down device connected between an input pad and an input terminal of an input buffer circuit. The step-down device prevents the input buffer circuit from being damaged by voltage signals provided to the input pad.
FIG. 1 is a schematic circuit diagram showing an example of a tolerant input circuit 100 in the prior art. An input pad 1 is connected to an input terminal of an input buffer circuit 2 via an N-channel MOS transistor Tr1. The gate of the transistor Tr1 is supplied with voltage from a power supply VDD, and the transistor Tr1 is kept constantly activated.
The input terminal of the input buffer circuit 2 is connected to the power supply VDD via an N-channel MOS transistor Tr2. The gate of the transistor Tr2 is connected to the input terminal of the input buffer circuit 2.
In the tolerant input circuit 100, when the input pad 1 is provided with a high level input signal having voltage that is higher than that of the power supply VDD, the transistor Tr1 functions to set an input voltage Va of the input buffer circuit 2 to VDD−Vth1 (Vth1 represents the threshold value of the transistor Tr1). Accordingly, the transistor Tr1 functions as a step-down device and restricts the input voltage Va to VDD−Vth or less.
The tolerant input circuit 100 decreases the input voltage Va of the input buffer circuit 2 to voltage that is less than the breakdown voltage of the input buffer circuit 2 even if the input voltage of the input pad 1 becomes higher than that of the power supply VDD.
Further, when the transistor Tr1 is kept activated, the input voltage Va may become higher than the voltage of the power supply VDD. However, if the input voltage Va becomes higher than the voltage of the power supply VDD for an amount corresponding to the threshold value Vth2 of the transistor Tr2 or greater, the transistor Tr2 functions as a diode. This restricts the input voltage Va to VDD−Vth2 or less.
In such a tolerant input circuit 100, differences resulting from fabrication process or differences in the ambient temperature may result in differences in the threshold value of the transistor Tr1. Due to the recent trend for lower power supply voltages, for example, when the power supply VDD is set to 2.5 V and the high level signal provided to the input pad 1 is set to 3 V, the input voltage Va of the input buffer circuit 2 may be decreased more than necessary because of the difference in the threshold value of the transistor Tr1.
In such a case, referring to FIG. 2, the voltage of an input signal Vah1 of the input buffer 2 becomes lower than the voltage threshold value Vx of the input buffer circuit 2. Thus, the input signal would not be recognized as having a high level and cause an anomaly.
Japanese Laid-Open Patent Publication No. 2004-304475 describes an inverter circuit that functions in accordance with the output voltage of a step-down device to drive a pull-up transistor and ensure the input voltage of a Schmitt inverter, which serves as an input buffer circuit.
Japanese Laid-Open Patent Publication No. 2000-228622 describes controlling the back gate voltage of one of the transistors of a CMOS inverter circuit to vary the threshold value of the transistor and adjust the duty of an output signal.